1. Field of the Invention
The present invention is generally directed to microprocessor devices. In particular, the present invention relates to microprocessor devices that accelerate the processing of a set of instructions.
2. Background
Conventional processor implementations use pipelines to maximize the utilization of processor resources in solving streams of instructions. In order to obtain larger gains, some processor implementations duplicate key components or entire pipelines to allow multiple instructions to be processed simultaneously. The downside of this approach is that when a stream of dependent instructions is received for processing, the processor is forced to wait for the result of the earlier instructions in order to begin processing the later instructions. This bottleneck results in inefficient usage of processing resources as, regardless of how many duplicate key components or pipelines are available, it is necessary to process the entire stream of dependent instructions one instruction at a time. Each instruction in the stream of dependent instructions must thereby wait for its dependency to be resolved before it can be executed.
The bottleneck effect caused by the execution of streams of dependent instructions is exacerbated when running a code base that includes numerous streams of dependent instructions, such as code bases used to implement the G.726 speech codec.
Accordingly, what is desired is a system and method that resolves the problem of bottlenecks associated with the processing of dependent instructions within a microprocessor.